/* File:  AIC3204utils.c
 * Author: mezzo forte
 * Purpose: provides code for controlling volume on the AIC3204
			and handling configuration
 * Last Edit: 2/22/2010 : Updated Names
 */
#include "AIC3204utils.h"
#include "mfutils.h"
#include "i2c.h"

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  AIC3204_regget                                      *
 *                                                                          *
 *      Return value of codec register regnum                               *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Int16 AIC3204_regget(  Uint16 regnum, Uint16* regval )
{
    Int16 retcode = 0;
    Uint16 cmd[2];

    cmd[0] = regnum & 0x007F;       // 7-bit Device Address
    cmd[1] = 0;

    retcode |= I2C_write( AIC3204_I2C_ADDR, cmd, 1 );
    retcode |= I2C_read( AIC3204_I2C_ADDR, cmd, 1 );

    *regval = cmd[0];
    wait_cycles( 10 );
    return retcode;
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  _AIC3204_rset( regnum, regval )                                         *
 *                                                                          *
 *      Set codec register regnum to value regval                           *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Int16 AIC3204_regset( Uint16 regnum, Uint16 regval )
{
    Uint16 cmd[2];
    cmd[0] = regnum & 0x007F;       // 7-bit Device Address
    cmd[1] = regval;                // 8-bit Register Data

    return I2C_write( AIC3204_I2C_ADDR, cmd, 2 );
}



Int16 AIC3204_init(void)
{
	
	AIC3204_regset( 0, 0 );      // Select page 1
    AIC3204_regset( 1, 1 );      // Reset codec
    AIC3204_regset( 0, 1 );      // Point to page 1
    AIC3204_regset( 1, 8 );      // Disable crude AVDD generation from DVDD
    AIC3204_regset( 2, 1 );      // Enable Analog Blocks, use LDO power
    AIC3204_regset( 0, 0 );
    /* PLL and Clocks config and Power Up  */
    AIC3204_regset( 27, 0x0d );  // BCLK and WCLK is set as o/p to AIC3204(Master)
    AIC3204_regset( 28, 0x00 );  // Data ofset = 0
    AIC3204_regset( 4, 3 );      // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
    AIC3204_regset( 6, 8 );      // PLL setting: J=8
    AIC3204_regset( 7, 7 );     // PLL setting: HI_BYTE(D)
    AIC3204_regset( 8, 0x80 );   // PLL setting: LO_BYTE(D)
    AIC3204_regset( 30, 0x88 );  // For 32 bit clocks per frame in Master mode ONLY
                               // BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
    AIC3204_regset( 5, 0x91 );   //?;PLL setting: Power up PLL, P=1 and R=1
    AIC3204_regset( 13, 0 );     // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
    AIC3204_regset( 14, 0x80 );  // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
    AIC3204_regset( 20, 0x80 );  // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
    AIC3204_regset( 11, 0x88 );  // Power up NDAC and set NDAC value to 8
    AIC3204_regset( 12, 0x82 );  // Power up MDAC and set MDAC value to 2
    AIC3204_regset( 18, 0x88 );  // Power up NADC and set NADC value to 8
    AIC3204_regset( 19, 0x82 );  // Power up MADC and set MADC value to 2
    /* DAC ROUTING and Power Up */
    AIC3204_regset( 0, 1 );      // Select page 1
    AIC3204_regset( 0xc, 8 );   // LDAC AFIR routed to HPL
    AIC3204_regset( 0xd, 8 );   // RDAC AFIR routed to HPR
    AIC3204_regset( 0, 0 );      // Select page 0
    AIC3204_regset( 64, 2 );     // Left vol=right vol
    AIC3204_regset( 65, 0);      // Left DAC gain to 0dB VOL; Right tracks Left
    AIC3204_regset( 63, 0xd4 );  // Power up left,right data paths and set channel
    AIC3204_regset( 0, 1 );      // Select page 1
    AIC3204_regset( 0x10, 0x3a );// Unmute HPL , 0dB gain
    AIC3204_regset( 0x11, 0x3a );// Unmute HPR , 0dB gain
    AIC3204_regset( 9, 0x30 );   // Power up HPL,HPR
    AIC3204_regset( 0, 0 );      // Select page 0
    wait_cycles( 100 );    // wait
    /* ADC ROUTING and Power Up */
    AIC3204_regset( 0, 1 );      // Select page 1
    AIC3204_regset( 0x34, 0x30 );// STEREO 1 Jack
		                       // IN2_L to LADC_P through 40 kohm
    AIC3204_regset( 0x37, 0x30 );// IN2_R to RADC_P through 40 kohmm
    AIC3204_regset( 0x36, 3 );   // CM_1 (common mode) to LADC_M through 40 kohm
    AIC3204_regset( 0x39, 0xc0 );// CM_1 (common mode) to RADC_M through 40 kohm
    AIC3204_regset( 0x3b, 0 );   // MIC_PGA_L unmute
    AIC3204_regset( 0x3c, 0 );   // MIC_PGA_R unmute
    AIC3204_regset( 0, 0 );      // Select page 0
    AIC3204_regset( 0x51, 0xc0 );// Powerup Left and Right ADC
    AIC3204_regset( 0x52, 0 );   // Unmute Left and Right ADC
    
    AIC3204_regset( 0, 0 );    
	return 0;
}

